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課程名稱 |
計算機結構
Computer Architecture |
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開課學期 |
99-2 |
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授課對象 |
電機資訊學院 電機工程學系 |
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授課教師 |
吳安宇 |
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課號 |
EE4039 |
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課程識別碼 |
901 43200 |
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班次 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
選修 |
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上課時間 |
星期五2,3,4(9:10~12:10) |
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上課地點 |
電二225 |
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備註 |
總人數上限：60人 |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
Chapter 1 Computer Abstractions and Technology
Chapter 2 Instructions: Language of the Computer
Chapter 3 Arithmetic For Computers
Chapter 4 Assessing and Understanding Performance of CPU
Chapter 5 The Processor: Data Path and Control-1
The Processor: Data Path and Control-2
Chapter 7 Large and Fast: Exploiting Memory Hierarchy-p1
Large and Fast: Exploiting Memory Hierarchy-p2
Chapter 6 Enhancing CPU Performance with Pipelining with concept of Chapter 5
Chapter 8 Storage, Networks, and Other Peripherals |
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課程目標 |
1.basic concept of RISC (Reduced Instruction Set Computer), compared with CISC (Complex Instruction Set Computer)
2.The Assembly/Machine language of the MIPS CPU
3.Detailed CPU design:
Instruction set
Data path
Control Unit
Arithmetic Logic Unit (ALU)
Techniques to enhance CPU performance, e.g., pipelining.
4.Memory hierarchy:
Cache: How to improve data/instruction access time?
Virtual memory: How to handle program/data that is larger than your physical (main) memory?
5.I/O peripherals:
Know more about I/O Devices.
How to transfer data directly from I/O devices to memory? Learn the technique of Direct Memory Access (DMA).
What is the relationship among CPU/Memory/I-O? |
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課程要求 |
Prerequisite:
Switch circuits and logic designs
Electronics |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
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參考書目 |
Textbook： (Main) “Computer organization and design: The hardware/software interface”,by D. A. Patterson and J. L. Hennessy, Morgan Kaufmann Publishers, 2009, 4th Edition (新月, 東華).
Reference： (Verilog Coding, optional)“Advanced Digital Design with the Verilog HDL,” by M. D. Ciletti, Prentice Hall, 2003.
(Verilog Coding, optional)“Verilog HDL: A Guide to Digital Design and Synthesis,” 2nd ed., by Samir Palnitkar, SunSoft Press, 2003 (全華)
(Verilog Coding, optional) “Verilog HDL: Degital design and modeling”, J. Cavanagh,
CRC Press, 2007.
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評量方式
(僅供參考) |
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